1. Field of the Invention
The present invention relates generally to methods and apparatus for assembling one or more semiconductor dice with a substrate. In particular, the present invention relates to methods and apparatus for electrically interconnecting a back side of one or more semiconductor dice to a carrier substrate and various assembly and stacking arrangements implemented using back side electrical interconnections of semiconductor dice.
2. State of the Art
Interconnection and packaging-related issues are among the factors that determine not only the number of circuits that can be integrated on a semiconductor die or “chip,” but also the performance of the chip. These issues have gained in importance as advances in chip design have led to reduced sizes of transistors and enhanced chip performance. The industry has come to realize that merely having a fast chip will not necessarily result in a fast system; the fast chip must also be supported by equally fast and reliable electrical connections. Essentially, on-chip connections, in conjunction with those of the chip's associated packaging, supply the chip with signals and power, provide signals from the chip and redistribute the tightly spaced or pitched terminals or bond pads of the chip to the terminals of a carrier substrate such as a printed circuit board.
Flip-chip technology, its fabrication and use are well known to those of ordinary skill in the art, as the technology has been in use for over 30 years and continues to develop. A flip-chip semiconductor device conventionally comprises a semiconductor die having an active surface having active integrated circuitry components formed therein and bearing contacts such as bond pads, and an opposing back surface or “back side” devoid of active components or, usually, of any components whatsoever. A dielectric layer, for example, of silicon dioxide or silicon nitride, is formed over the active surface by techniques well known in the art. Apertures are defined in the dielectric layer (also termed a passivation layer), for example, using well-known photolithographic techniques to mask and pattern the dielectric layer and etch the same, for example, with buffered HF to expose the contacts or bond pads on the active surface. The bond pads may be respectively connected to traces of a redistribution layer on the dielectric layer in the form of redistribution lines, i.e., power, ground and signal lines, in a well-known manner, for example, by evaporating or sputtering a layer of aluminum or an alloy thereof over the passivation layer, followed by masking and etching to define the traces. The redistribution lines of the redistribution layer enable the external connections of the semiconductor device provided by the relatively compact arrangement of closely spaced or pitched bond pads to be distributed over a larger surface area with wider spacing or pitch between external connections to higher-level packaging. Solder bumps, or balls, are typically placed upon a pad located at an end of each redistribution line to enable electrical coupling with contact pads or terminals on the higher-level packaging, typically comprising a carrier substrate, such as a printed circuit board. The flip-chip semiconductor device, with the solder bumps on its active surface, is “flipped” and attached face down to a surface of the carrier substrate, with each solder bump on the semiconductor device being positioned on the appropriate contact pad or terminal of the carrier substrate. The assembly of the flip-chip semiconductor device and the carrier substrate is then heated so as to reflow the solder bumps to a molten state and thus connect each bond pad on the semiconductor device through its associated redistribution line and solder bump to an associated contact pad or terminal on the carrier substrate.
Because the flip-chip arrangement does not require leads of a lead frame or other carrier structures coupled to a semiconductor die and extending beyond the lateral periphery thereof, it provides a compact assembly in terms of the semiconductor die's “footprint” on the carrier substrate. In other words, the area of the carrier substrate within which the contact pads or terminals are located is, for a given semiconductor die, the same as or less than that occupied by the semiconductor die itself. Furthermore, the contacts on the die, in the form of widely spaced or pitched solder bumps, may be arranged in a so-called “area array” disposed over substantially the entire active surface of the die. Flip-chip bonding, therefore, is well suited for use with dice having large numbers of I/O contacts, in contrast to wire bonding and tape-automated bonding techniques which are more limiting in terms of the number of bond pads which may reasonably and reliably be employed. As a result, the maximum number of I/O contacts and power/ground terminals available can be increased without substantial difficulty, and signal and power/ground interconnections can be more efficiently routed on the semiconductor die. Examples of methods of fabricating semiconductor die assemblies using flip-chip and other techniques are described in U.S. Pat. No. 6,048,753 to Farnworth et al., U.S. Pat. No. 6,018,196 to Noddin, U.S. Pat. No. 6,020,220 to Gilleo et al., U.S. Pat. No. 5,950,304 to Khandros et al., and U.S. Pat. No. 4,833,521 to Early.
As with any conductive line carrying a signal, the redistribution lines for integrated circuits generate electromagnetic and electrostatic fields, or “cross-talk.” These electromagnetic and electrostatic fields may affect the signals carried in adjacent redistribution lines unless some form of compensation is used. Examples of redistribution lines formed over the active circuitry in a flip-chip semiconductor device that disclose methods of limiting cross-talk are illustrated in U.S. Pat. Nos. 5,994,766 and 6,025,647, each to Shenoy et al.
Electromagnetic and electrostatic coupling between redistribution lines, or cross-talk, is undesirable because it increases the impedance of the redistribution lines and may create impedance mismatching and signal delays. Significant factors affecting cross-talk between adjacent redistribution lines include redistribution line length, the distance between the adjacent redistribution lines and the dielectric constant (ετ) of the material between the adjacent redistribution lines. For flip-chip devices, where a large number of bond pads with associated redistribution lines on the active surface are used to carry signals to and from various external connection locations with higher-level packaging for convenient access, impedance can be a significant factor affecting the speed of the system. The location of redistribution lines on the active surface also severely limits the location, size and number of passive circuit elements such as resistors, capacitors and inductors which may be used to compensate for cross-talk or otherwise enhance performance of the packaged semiconductor device without undesirably enlarging the size thereof. Further, such impedance problems affecting the speed of the semiconductor device are only compounded when stacking multiple flip-chip devices.
Therefore, it would be advantageous to prevent cross-talk between adjacent redistribution lines on the active surface of a flip-chip configured semiconductor die while also maintaining a large number of available, widely spaced or pitched I/O terminals and, further, maintaining or even reducing the size of the semiconductor die and associated footprint. It would also be advantageous to provide a flip-chip configured semiconductor die that offers improved stacking capabilities without compounding impedance problems, may be tailored to provide physical and thermal stress relief, and may be configured to provide enhanced resistive, inductive and capacitive electrical characteristics to the packaged semiconductor die.